1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices, and more particularly, to a non-volatile semiconductor memory device carrying out programming, erasing, and the like with a p channel type memory cell.
2. Description of the Background Art
A flash memory which is one kind of a non-volatile semiconductor memory device is the most promising memory device for the next generation because of its manufacturing cost lower than that of a dynamic random access memory (DRAM).
Memory cells constituting the flash memory each generally include an n type source region and an n type drain region formed in the surface of a p type region, a floating gate electrode (electric charge storage electrode) formed on a channel region sandwiched by the source region and the drain region with a tunnel oxide film interposed therebetween, and a control gate electrode (control electrode) formed on the floating gate electrode with an insulating film interposed therebetween.
In each memory cell, a source line is connected to the source region. A bit line is connected to the drain region. The floating gate electrode stores information. A word line is connected to the control gate electrode.
A programming operation and an erasing operation of an NOR type flash memory will now be described with reference to FIGS. 32 and 33. In the programming operation, a voltage of approximately 5 V is applied to a drain region 33, and a voltage of approximately 10 V is applied to a control gate 37, as shown in FIG. 32. A source region 32 and a p well 31 are kept at a ground potential (0 V).
At this time, there is a current flow of several hundreds .mu.A through the channel of the memory cell. An electron accelerated in the vicinity of drain region 33 among electrons moving from source region 32 to drain region 33 is turned into an electron having high energy, that is, a so-called channel hot electron, in this vicinity. This electron is injected into a floating gate electrode 35, as indicated by arrow A in the figure, by an electric field generated by the voltage applied to control gate 37. Thus, electrons are stored in floating gate electrode 35, and a threshold voltage V.sub.th of the memory cell attains 8 V, for example. This state is referred to as a programmed state, "0".
Then, the erasing operation will be described with reference to FIG. 33. A voltage of approximately 5 V is applied to source region 32, a voltage of approximately -10 V is applied to control gate electrode 37, and p type well 31 is maintained at the ground potential. At this time, drain region 33 is brought to an open state. An electron in floating gate electrode 35 passes through thin tunnel oxide film 34 by an FN tunneling phenomenon caused by an electric field generated by the voltage applied to source region 32, as indicated by arrow B in the figure. Thus, the threshold voltage V.sub.th of the memory cell attains 2 V, for example, by ejection of electrons in floating gate electrode 35. This state is referred to as an erased state, "1".
Other than the above described NOR type flash memory which carries out programming by the channel hot electrons and erasing by the FN tunneling phenomenon, various kinds of flash memories have been developed which consume less current at the time of programming and erasing, because they operate based on a single power source. A DINOR (divided bit line NOR) flash memory described in "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory," IEEE Journal of Solid-State Circuits, (Vol. 29, No. 4, April 1994): 454-460, or "Improved Array Architectures of DINOR for 0.5 .mu.m 32M and 64M bit Flash Memories," IEICE Trans. Electron, (Vol. E77-C, No. 8, August 1994): 1279-1286 is one of them.
This DINOR type flash memory's structure and its operation principle will now be described with reference to FIGS. 34 to 36. Similar to the case of the above described memory cell of the NOR type flash memory, a memory cell of this DINOR type flash memory includes n type source region 32 and n type drain region 33 formed in the surface of p well 31. Floating gate electrode 35 is formed on the channel region sandwiched by source region 32 and drain region 33 with tunnel oxide film 34 interposed therebetween. Control gate electrode 37 is formed on floating gate electrode 35 with an insulating film 36 interposed therebetween.
The above structured memory cell is generally referred to as a stacked gate type memory cell. Source regions 32 are electrically connected in common in all memory cells or in a block formed of a predetermined number of memory cells. A word line is connected to control gate electrode 37, and a bit line is connected to drain region 33. A predetermined word line and a predetermined bit line are selected in such a structure, so that a predetermined memory cell is selected.
The programming operation will first be described with reference to FIGS. 34 to 36. In the programming operation, a negative voltage of approximately -8 V to approximately -11 V is applied to control gate electrode 37, and a positive potential of approximately 4 V to approximately 8 V is applied to drain region 33. At this time, p well 31 is kept at the ground potential (0 V), and source region 32 remains open. During this state, a strong electric field is applied to tunnel oxide film 34 in a region where floating gate electrode 35 and drain region 33 overlap each other. This application of the strong electric field causes the FN tunneling phenomenon, and electrons are injected from floating gate electrode 35 to drain region 33 through tunnel oxide film 34. This programming operation brings the memory cell to "Low Vt" (low Vth state).
On the other hand, in the erasing operation, a positive potential of approximately 8 V to approximately 12 V is applied to control gate electrode 37, a negative potential of approximately -6 V to -11 V is applied to source region 32 and p well 31, and drain region 33 is maintained open. In this state, a channel layer of an electron 38 is formed in the channel portion of the memory cell and a strong electric field is applied to tunnel oxide film 34 between the channel layer and floating gate electrode 35. This strong electric field causes the FN tunneling phenomenon, and electron 38 of the channel layer is injected into floating gate electrode 35. This erasing operation brings the memory cell to "High Vt" (high Vth state).
In a reading operation, a positive potential of about 3 V to 5 V which is approximately intermediate between "Low Vt" and "High Vt" is applied to control gate electrode 37, source region 32 and p well 31 are grounded, and a positive potential of about 1 V to about 2 V is applied to drain region 33, so that it is confirmed whether or not there is a current flow through the memory cell. Based on this confirmation, it is determined whether the memory cell is in a state of "High Vt" or "Low Vt".
FIG. 37 is a diagram representing programming characteristics of the above described memory cell of the DINOR type flash memory, indicating that the threshold value becomes smaller in a positive range as a programming time becomes longer. FIG. 38 shows erasing characteristics of the above described memory cell of the DINOR type flash memory, indicating that the threshold value of the memory cell becomes larger in a positive range as an erasing time becomes longer.
The above described conventional DINOR type flash memory has the following problem.
In the programming operation of the DINOR type flash memory, such potential application conditions as shown in FIGS. 34 and 36 are used. More specifically, p well 31 is grounded, source region 32 is brought to an open state, and a positive potential and a negative potential are applied to drain region 33 and control gate electrode 37, respectively, whereby electron 38 is drawn to drain region 33 from floating gate electrode 35.
This ejection of electrons uses the same phenomenon as was used in the erasing operation of the DINOR type flash memory described in "A 5 Volt Only 16M bit Flash EEPROM Cell with a Simple Stacked Gate Structure," IEDM Technical Digest (1990): 115-118 or explained with reference to FIG. 33. A method of ejecting electrons into an n type impurity diffusion layer is described in "Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction," (Symp. VLSI Tech., 1993): 81-82, for example.
In the above described DINOR type flash memory, for example, a strong electric field is applied between floating gate electrode 35 and drain region 33, as shown in FIG. 39. Therefore, a band-to-band tunneling phenomenon occurs in p well 31 in the vicinity of drain region 33. As a result, an electron-hole pair 40 is produced in drain region 33, causing a drain leakage. This drain leakage is referred to GIDL (Gate Induced Drain Leakage).
Electron 38 of electron-hole pair 40 produced by the band-to-band tunneling phenomenon is drawn to drain region 33 supplied with a positive potential. On the other hand, a hole 39 is pulled in the channel direction, and flows towards p well 31. Since hole 39 is accelerated by a depletion layer electric field between drain region 33 and p well 31 to obtain high energy (which is called a hot hole), a part of holes 39 are injected into tunnel oxide film 34.
The influence of hole 39 on tunnel oxide film 34 has been widely studied from the standpoint of reliability of a gate oxide film in an MOSFET. It is generally confirmed that hole 39 does serious damage to tunnel oxide film 34.
According to a close study described in "Oxide Breakdown Model for Very Low Voltages," Symp. VLSI Tech. (1993): 43-44, for example, there is a close correlation between the lifetime of TDDB of a silicon oxide film used as a gate insulating film and a total amount of holes which pass through the film upon application of a voltage. From the standpoint of reliability of data retention characteristics of a flash memory, it is reported in recent years that a leakage current of a gate oxide film at a low voltage is increased by injection of hot holes into the gate oxide film. This is described in "Analysis of Excess Current Induced by Hot-Hole Injection into Thin SiO.sub.2 Films," Proceedings of the 42nd Lecture Meetings Related to Applied Physics (No. 2, 28a-C-10): 656, for example.
As described above, the problem in the memory cell of the conventional DINOR type flash memory is that the potential application conditions under which GIDL is likely to be generated are employed during the programming operation. As a result, hot holes are injected into the tunnel oxide film at the time of programming, causing a marked deterioration of the tunnel oxide film (cf. K. Tamer San, et al. "Effect of Erase Source Bias On Flash EPROM Device Reliability," IEEE Transactions on Electron Devices (Vol. 42, No. 1, January 1995): 150.
In recent years, an electric field relaxation layer 41 having a gentle n.sup.- impurity distribution is formed so as to surround drain region 33, as shown in FIG. 40 for example, in order to suppress the above-described deterioration of the tunnel oxide film by injection of hot holes. Provision of electric field relaxation layer 41 allows relaxation of the lateral electric field in drain region 33 which draws electrons from floating gate electrode 35 by the FN tunneling phenomenon.
However, formation of electric field relaxation layer 41 has a disadvantage of a small effective gate length L.sub.1, since an overlap length L between an impurity diffusion layer and floating gate electrode 35 becomes longer. Electric field relaxation layer 41 causes punch-through even in a memory cell having a longer effective gate length, when the memory cell is miniaturized.
Therefore, the memory cell of the conventional DINOR type flash memory cannot be miniaturized, hampering high integration of memory cells in a memory cell array.